The present invention generally relates to signal processors, and more particularly to a signal processor that is used for a digital processing of an analog signal and has a construction suitable for assembling into an integrated circuit.
In relation to the high resolution, low cost AD/DA converters, the signal processing that uses the oversampling technique and delta-sigma modulation is proposed.
FIG. 1 shows an example of such a signal processing as applied for magnifying an analog signal by a predetermined factor. The system of FIG. 1 includes an A/D conversion unit 51 for converting an analog input signal A to a digital signal A.sub.1, a processing unit 52 for applying a digital multiplication process on the digital signal A.sub.1 to produce a digital signal C.sub.1, and a D/A conversion unit 53 for converting the digital signal C.sub.1 to an analog signal C.
The A/D conversion unit 51 includes an analog filter 54 for filtering the input analog signal A, an analog delta-sigma modulator 55 for producing one-bit PDM data from the analog signal supplied from the filter 54 by an oversampling process, and a decimation filter 54 supplied with the one-bit PDM data of the delta-sigma modulator 55 for reducing the sampling rate by converting the one-bit data to multiple-bit PCM data. In a typical example, a sampling rate of 7.68 M samples/sec is used in the delta-sigma modulator 55, while the decimation filter reduces the sampling rate for example to 48 k samples/sec to form the foregoing digital PCM data A.sub.1. The PCM data A.sub.1 may be 16 bit-data. Typically, the output PDM data of the delta-sigma modulator 55 produces a bipolar pulse train wherein the density of the positive pulses and the negative pulses changes in response to the input analog signal A.
The processing unit 52 includes a usual digital multiplier circuit 62 that applies a predetermined constant to the digital signal A.sub.1. The multiplier circuit 62 supplies the result of processing to the D/A conversion unit 53 as the multiple-bit digital data C.sub.1.
The D/A conversion unit 52 includes a zero-interpolation circuit 57, a digital low pass filter 58, a digital delta-sigma modulator 59, a one-bit D/A converter 60, and an analog low-pass filter 61. There, the zero interpolation circuit 57 is supplied with the digital signal C.sub.1 and applies an oversampling process upon the signal C.sub.1. Thereby, the sampling rate is increased to 7.68 M samples/sec. The digital low-pass filter 58 is supplied with the output of the zero-interpolation circuit 57 and eliminates the alias components that appear in each 48 kHz interval. Further, the digital delta-sigma modulator 59 is supplied with the output of the digital low-pass filter 58 and converts the same to one-bit PDM data. The one-bit PDM data thus produced by the delta-sigma modulator 59 is then supplied to the one-bit D/A converter 60 for D/A conversion. Finally, the output analog signal produced by the one-bit D/A converter 60 is passed through the analog low-pass filter 61, and the output analog signal C is obtained. By combining the oversampling process and delta-sigma modulation, the system of FIG. 1 can provide a multiplication of analog signals with an improved precision or resolution.
FIG. 2 shows another example of the use of the oversampling and delta-sigma modulation for adding analog input signals A and B.
Referring to FIG. 2, the system includes an A/D conversion unit 61 supplied with the analog input signals A and B for converting the same to digital signals A.sub.1 and B.sub.1, a processing unit 62 supplied with the digital signals A.sub.1 and B.sub.1 for adding the same to produce a digital output signal C.sub.1, and a D/A conversion unit 63 supplied with the digital output signal C.sub.1 for producing an analog output signal C.
There, the A/D conversion unit 61 includes a first channel for processing the input signal A and a second channel for processing the input signal B, wherein the first channel includes an analog filter 64a corresponding to the analog filter 54 of FIG.1 for filtering the input analog signal A. The analog signal A thus passed through the filter 64a enters into an analog delta-sigma modulator 65a corresponding to the delta-sigma modulator 55 of FIG.1 and is converted to one-bit PDM data. This one-bit PDM data is supplied to a decimation filter 66a corresponding to the decimation filter 56 of FIG.1 wherein it is converted to multiple bit PCM data upon decimation. The output of the decimation filter 66a is supplied to the processing unit 62 as the digital signal A.sub.1.
The second channel has a substantially identical construction and includes an analog filter 64b, an analog delta-sigma modulator 65b, and a decimation filter 66b. As the construction and function of the second channel are substantially identical with those of the first channel, further description thereof will be omitted. The second channel outputs PCM data B.sub.1 in correspondence to the input analog signal B.
The processing unit 62 includes a digital adder circuit 72 for adding the input PCM data A.sub.1 and B.sub.1. Thereby, the adder circuit 72 produces output PCM data C.sub.1.
The D/A conversion unit 63 has a construction substantially identical with the D/A conversion unit 53 of FIG.1 and includes a zero-interpolation circuit 67 corresponding to the zero-interpolation circuit 57, a digital low pass filter 68 corresponding to the digital low pass filter 58, a digital delta-sigma modulator 69 corresponding to the digital delta-sigma modulator 59, a one-bit D/A converter 70 corresponding to the one-bit D/A converter 60, and an analog low-pass filter 71 corresponding to the analog low-pass filter 61. As the construction and function of the unit 63 are substantially identical with those of the unit 53, further description will be omitted.
In any of the systems of FIG. 1 and FIG. 2, one can achieve a high precision processing by the use of the oversampling process in the delta-sigma modulator. More specifically, one can suppress the quantum noise associated with the analog-to-digital conversion by using a very large sampling rate as compared with the Nyquist frequency as is well known in the art. Thus, the signal processing system of FIG. 1 or FIG. 2 is suitable for a high precision and high resolution digital processing of analog signals and finds applications in various fields such as telecommunications, audio systems, voice synthesis, etc.
In the signal processing system of FIG. 1 or FIG. 2, it should be noted that the digital filters such as the decimation filters 56, 66a, 66b used for processing the output of the delta-sigma modulator or the digital low-pass filters such as the filters 58 and 68 that processes the digital PCM data to be supplied to the digital delta-sigma modulator are the essential device. When the design of these digital filters is inappropriate, there may be a case wherein an alias noise is mixed in the output analog signal C. Further, the digital filters may cause a delay in the output. In order to avoid these problems, one has to use a complex construction for the digital filters. On the other hand, such a complex construction of the digital filters raises a problem of assembling the system as an integrated circuit.